The present technique relates to an apparatus and method for maintaining address translation data within an address translation cache.
It is known to provide data processing systems which incorporate one or more distinct types of address translation cache. For example an address translation cache such as a translation lookaside buffer (TLB) may be used to store address translation data that identifies a full translation from a virtual address to a physical address. However, as another example of address translation cache, a walk cache may be provided that stores address translation data that identifies a partial translation of a virtual address, which can be useful in improving performance by reducing the number of slow page table walks required. Such a walk cache is typically provided as a separate structure to a TLB. Alternatively, a single physical storage structure such as random access memory (RAM) may be used to support the provision of both a walk cache and a TLB, but with a hard partitioning of the resources between those resources used for the TLB and those resources used for the walk cache.
Such address translation caches consume significant circuit resources, and accordingly it is desirable that efficient use be made of the capacity of the resources used for address translation caching.